1. Field of the Invention
The present invention relates to a semiconductor device with a multi-level interconnection structure, and more particularly, to multi-level interconnects in which wires are formed in upper layers above a semiconductor substrate provided with a semiconductor component.
2. Description of the Prior Art
FIG. 9 is a sectional view illustrating a construction of a conventional semiconductor device with a multi-layer interconnection structure. FIG. 10 is a sectional view illustrating a schematic construction in a fuse of a conventional semiconductor device with a multi-level interconnection structure. In the drawings, reference numeral 101 denotes a semiconductor device with a multi-level interconnection structure, numeral 2' denotes a 20 semiconductor substrate, numeral 3' denotes a memory region such as a DRAM block, numeral 4' denotes a peripheral circuit region such as a logic block, numeral 5' denotes a stacking memory cell of DRAM as a semiconductor component created in the memory regions 3', numerals 6a', 6b' denote transistors such as NMOS and PMOS formed in the peripheral region 4', numerals 61'-63' denote dielectric films, numerals C1', C2' denote contacts, and numeral 7' denote multilevel interconnects which are constructed in the upper layers over the DRAM memory cell 5'.
In the DRAM memory cell 5', reference numeral 11' denotes a bit line made of a refractory metal such as tungsten, or polysilicon, numeral 12' denotes a word line constituting a silicide with a refractory metal such as tungsten and molybdenum, numeral 13' denotes a cell plate made of polysilicon, numeral 14' denotes a storage node made of polysilicon as well, and numeral 15' denotes a dielectric layer intervening between the cell plate 13' and the storage node 14', and the dielectric layer 15' is constituted by a multi-layered film with nitride and oxide films.
In the multi-level interconnects 7', reference numeral 71' denotes a first interlayer dielectric, numeral 72' denotes a second interlayer dielectric, numeral 73' denotes a third interlayer dielectric, numeral 21' denotes a first metal wire, numeral 22' denotes a second metal wire, numeral 23' denotes a third metal wire, numeral 24' denotes a fourth metal wire, and reference symbols V1'-V3' designate via contacts formed in the interlayer dielectrics 71'-73' respectively, and for electrically interconnecting with the upper and lower metal wires, the via contacts V1'-V3', typically made of aluminum or aluminum alloys, as well as the metal wires 21'-24'.
In addition, reference numeral 31' denotes a fuse formed in the same layer as the third metal wire 23' as a component of the multi-level interconnects 7' in the vicinity of the boundary of the memory region 3' and the peripheral circuit region 4'. The fuse 31' is used for replacing a defective DRAM memory cell 5' caused in the manufacturing processes with a redundancy memory cell.
FIG. 9 illustrates one example of a construction of a semiconductor device with a multi-level interconnection structure, and designates that a memory including a DRAM memory cell as a component is formed in the memory regions 3' and that a peripheral circuit including the transistors 6a', 6b' as a component in the peripheral circuit region 4'. In FIG. 9, a part of the components of the DRAM memory cell 5' and transistors 6a', 6b' is abbreviated (as not shown). Additionally the hatching in FIGS. 9 and 10 is partially abbreviated for simplicity.
A description will now be given of the operation. When the defective DRAM memory cell 5' caused in the manufacturing processes is replaced with a redundancy memory cell, first a wafer test is executed, and then a laser beam P is applied to the fuse 31' to be blown based on the test results as shown in FIG. 11. When the laser beam P is applied to the fuse 31', the energy of the laser beam P is absorbed in the fuse 31', to be fused and blown. As a result, the redundancy circuit becomes available. Thus, the defective DRAM memory cell 5' may be replaced with the redundancy memory cell.
There are the prior arts disclosed in the patent documents of Japanese patent laid open publication numbers JP-A-60/76140 and JP-A-9/17877 for reference of the present invention.
FIG. 12 is a sectional view illustrating a fuse in a semiconductor device in JP-A-60/76140. In the drawing, reference numeral 111 denotes a semiconductor device, numeral 112 denotes a semiconductor substrate, numeral 113 denotes a field oxide film, numeral 114 denotes a fuse, numeral 115 denotes a PSG (phosphosilicate glass) film covering the fuse 114, numeral 116 denotes a conductive layer formed on the field oxide film 113 below the fuse 114, and numeral 117 denotes a dielectric film formed between the fuse 114 and the conductive layer 116.
In the art, it is assumed that the fuse 114 and the conductive layer 116 are formed by polysilicon, a refractory metal, or a silicide compound thereof, and are formed simultaneously during the formation of word lines or bit lines as a component of memory cells. However, the conductive layer disposed below the fuse 114 is merely one layer, illustrating a mono-layer wiring structure.
FIG. 13 is a sectional view illustrating a fuse of a semiconductor device in JP-A-9/17877. In the drawing, reference numeral 121 denotes a semiconductor device, numeral 122 denotes a fuse, and numeral 123 denotes a conductive layer formed below the fuse 122. In the art, the conductive layer 123 is merely used as a means for reflecting laser beams.